application note AN102 AN102-1 design issues in high speed spi (hsspi) serial eeprom by ray kahidi introduction the availability of higher density serial eeproms means they are being designed into applications that were con- sidered far fetched just a few years ago. in many instances serial eeproms have replaced their byte wide counter parts as the ideal nonvolatile storage device. the increased capacity demands the transfer of larger blocks of information. a major bottleneck is the transfer speed of the interface between the eeprom and the con- troller. the new generation of spi serial devices from xicor attempt to remedy the problem by increasing the date transfer rate to 5mhz. this application note discusses the implementation of sys- tems based on various microcontrollers which are capable of 5mhz sustained throughput on the spi bus. the key benefit of higher throughput and reduced transfer time is higher system reliability. during system power fail- ures the microprocessor has a limited time to finish its cur- rent task and save all the important system parameters to the eeprom. the improved sp eed can quickly transfer up to 32 bytes to the internal buffer of the eeprom. in some cases (i.e. powerpc processors) the above opera- tion is transparent to the cpu, after the buffer address and transfer byte count are set prior to starting the spi controller. advanced features integrated on the hsspi serial eeproms include the block lock, which allows write con- trol to guard against inadvertent or unauthorized write operations. this is ideal for protecting sensitive data (i.e. kernel, setup parameters, security keys, id numbers, serial numbers). the status register is a great way to monitor performance of the device. when read, it returns information on the state of the internal write operations. by monitoring the wip bit the software can detect an early end of write, instead of waiting the maximum specified write time after the last byte was transferred to the device. the spi bus has many advantages over other commonly employed serial buses. one major benefit is that most microcontrollers have hardware capability to directly inter- face to the spi bus as the master. this reduces the soft- ware overhead required to operate the interface and frees up the cpu to handle other tasks at hand. improved upload time in the hsspi is apparent here by evaluating the result of comparison at different transfer clock rates: powerpc micro p rocessors and dsps the systems that can greatly benefit from the high speed spi are products based on the high performance micro- processors or dsps. the spi port on the powerpc processors (mpc821/23/ 60) is versatile. the clock rate is programmable to run at 5mhz using a 25mhz system clock. the clock control reg- ister allows modification of the clock phase and polarity to match the peripheral device. multiple transmit and receive buffers can be initialized for automatic process by the spi module, freeing up the main cpu. presence of slow devices on a fast spi bus forces the master controller to reload its baud rate generator with a new value anytime it communicates with that device. this lowers the overall system performance by increasing software overhead and time delays. clock size u p load time 100khz 64kb 327.68ms 2mhz 64kb 32.77ms 5mhz (hsspi) 64kb 13.11ms spiclk spimiso spimosi mpc821/23/60 x25650 25mhz cs so sck si cs powerpc
xicor application note AN102-2 AN102 there are a few dsp products in the market with on chip, fast spi ports. one, the motorola dsp56002, has a syn- chronous serial interface(ssi) port that can be configured to interface with an spi type device. this is done by selecting the synchronous mode, gated clock-on and on- demand mode. the programmable baud rate generator allows setting the transfer rate to 5 mhz. the interface is double byte buffered and requires extensive interface soft- ware for continuous data flow. 68hc16 qspi the qspi port on the m68hc16 is versatile with program- mable baud rate option. using a 16mhz system clock the clock speed can be programmed to operate at up to 4.1 mhz. the internal dual port ram is split into three seg- ments; command queue, transmit and receive buffers. all the cpu has to do is to refresh the command and transmit buffers and qspi takes care of the rest. the qspi timing is programmable, xicors high speed spi serial devices work in either mode 0 (sck clock idle state is low, input data is latched on the leading edge of the clock and output data is changed on the following edge) or mode 1 (sck clock idle state is high, output data is changed on the leading edge of sck and input data is latched on the fol- lowing edge of sck). the 68hc16 has four peripheral chip select (pcs0:3) pins that can be controlled by bit fields in the commands byte. general purpose synchronous communications port-mcs196, mcs251, mcs51 most microcontrollers are equipped with uarts which support synchronous communications mode. in the mcs251, mcs51 and mcs196 families the uart, in mode 0, configures the txd pin to output eight clock pulses and the rxd pin to function as a bidirectional data i/o. in the mcs51 and mcs251, the maximum clock rate is 1/12 of system clock. the mcs196 clock rate can be set to 4mhz using a 16mhz system clock. for half-duplex spi operation the si and so pins of the serial memories can be tied together txd rxd mcs196 x25650 16mhz cs si sck so cs
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